1. Field of the Invention
The present invention relates to a wafer scale integration (WSI) device, more particularly, to a wafer scale integration device using a bonding wire for supplying power supply voltages or common signals to a plurality of chips formed on the wafer.
The wafer scale integration device is used for a memory, a logic circuit and the like. In such a wafer scale integration device, for example, a power supply line is formed by bonding wires, since the power supply line should have low impedance characteristics and a bonding wire has low impedance characteristics. Furthermore, the bonding wire is not only used for the power supply line, but also a common signal line which requires low impedance characteristics.
2. Description of the Related Art
Recently, a wafer scale integration device, which is used for a memory, a logic circuit and the like, has been developed and prototype devices has been provided. In the wafer scale integration device, a plurality of circuits are integrated in all regions of the wafer. For example, in a wafer scale memory device which is one kind of a wafer scale integration device, a wafer includes an array of chips each having a memory circuit and additional control logic circuit.
In the art of wafer scale integration, the following merits are provided. First, a larger scale circuit can be integrated on the wafer than any other large scale integrated circuit (LSI). Next, a signal delay time can be shortened, since a mutual wiring distance between circuits becomes shorter by integrating a system on one piece of wafer. Further, reliability of the system can be improved by compensating for defective chips of the wafer or defective portions in the chip, and reliability of mounting can be improved by decreasing assembling processes.
As described above, the wafer scale integration device is suitable for constituting a monolithic memory or a repeated logical circuit including a plurality of basic configurations. In the monolithic wafer scale integration device, a circuit should be integrated in all regions in the wafer which may include defective portions, and thus the method of constituting the system by providing redundancy and bypassing the defective chips of the wafer or defective portions of the chip becomes indispensable to increasing the effective production yield to a practical level.
For example, in the wafer scale memory device, when a direction of a main orientation flat is assumed as an X-direction and a direction of crossing at a right angle to the main orientation flat is assumed as a Y-direction, each of the X-direction and Y-direction between neighboring chips are connected by local lines. When a signal is applied to an input of the wafer scale memory device, the signal bypasses defective chips and passes only operative chips serially, and appears at an output of the wafer scale memory device. Further, in the Y-direction, global lines each consisting of a command line (CMND) and a wafer clock line (WCK), Vcc lines, Vss lines, and V.sub.BB lines are connected in parallel by each chip array. Related art of the wafer scale integration device is disclosed in Japanese Patent Publication Nos. 58-18778 and 62-6267. Note, each of the above chips is not connected directly by the local lines, but a logic circuit is inserted therebetween.
It should be noted that the term "chip" here is used to mean a unit for forming a unit functional block like a unit memory block which is formed on a wafer to occupy a separate unit area and is connectable to adjacent one by a conductor pattern and/or a wire, but is not used to mean a physically independent unit severed from a wafer.
The wafer is cut into a square shape by cutting along the X-direction and Y-direction at the periphery thereof except for the corners, and the cut wafer is mounted on a base member called a carrier for actual use. Further, as known by persons with ordinary skill in the art, the operative chips are connected in serial bypassing defective chips, in a construction called a SPIRAL path.
In the wafer scale integration device, a mutual wiring distance of each of the chips becomes short in a plurality of diced chips connected by wirings. But, when power supply lines such as Vcc lines or Vss lines are constituted by metal wiring made of aluminium, a problem arises since resistance values of the metal wiring is large. Namely, the power supply lines are used for supplying power supply voltages of Vcc or Vss to a plurality of chips, a potential drop in supplied voltages is caused by the large resistance values of the metal wirings, and thus some chips may not be supplied with a sufficient potential of the power supply voltages of Vcc or Vss. Another problem arises in a cutting region of the wafer cut by a cutting blade. And further, when the global lines and the local lines are constituted by metal wiring made of aluminium and the like, a problem arises that these lines may be short-circuited by the circumference of the wafer.